Explain the machine instruction cycle.


Teaching Note:

This should include the role of data bus and address bus.


Sample Questions - FORMER CURRICULUM:

4. Describe how the computer carries out a machine instruction. [4 marks]


Before getting into the machine instruction cycle, a bit on the teaching note point - reacalling that we already looked briefly at the data bus and the address bus in 2.1.1.

So recall that the address bus is the path through which the CPU goes to specific addresses in memory to fetch stuff from RAM.

Once at that RAM address, the data that is found there is returned to the CPU via the data bus.



Machine Instruction Cycle

At a basic level, the machine instruction cycle is typically stated as:


Bit it can help to include an optional step for when what is fetched is an address - which is often the case. So there are really two possibilities as the cycle cycles:

A. When what is fetched is actually an address:

- fetch (from the RAM, found via the address bus, brought back via the data bus)

- decode (and realize that what was fetched was an address)

- fetch the data at the address which was just fetched

- decode (this will now be data/instructions, rather than an address)

- execute

- store result

(perform next fetch)

B. When what is fetched is data or instructions

- fetch (from the RAM, found via the address bus, brought back via the data bus)

- decode

- execute

- store result

(perform next fetch)


Now a bit more about each part of the cycle, without going into too many details, but not as detailed as the following video.

fetch - going to get data or instruction from the RAM and bringing them back to the CPU , remembering, particularly since it's the teaching note: from the RAM via the address bus, brought back via the data bus

decode - figure out what the instruction is, and how the particular CPU can execute such an instruction (such as ADD)

execute - that's where the Control Unit shuffles things into Arithmetic Logic Unit and the results out of it

store result - this may or may not be storing a final result to secondary storage, rather usually it's just storing the partial thing which has just been accomplished, such as adding a number to an ongoing calculation


The above is all you really should need to know for this assessment statement. But to help you put it all together, feel free to look through the following video, which goes to a level that is for sure beyond what you need for IB CS.


And for the fine details, here you go...

Fetch and Execute Example Video Explanation

(*** Note that there is a strange video editing glitch where the screen goes black for a bunch of seconds, but nothing is missed, so when it happens, at around the 6 minute mark, fast forward to around the 7:22 mark.)

** And also note that the following diagrams and video are "to be taken with a grain of salt", meaning that they give general indicaitons of how things work, without always being true to the actual functioning at a logic gate level.

A good companion to some of this would be the PBS Crash Course CS videos, in around # 4 and # 5 in the series.

(JSR: Could, at this point, download a simple computer from Minecraft Redstone and mirror using it with the diagram explanation video above)


These diagrams break the fetch and execute cycle into the specifics of just what is going on.











There is even less need for you to take a look at the following, but because all of this is a quite complicated, if you're interested, you my read on, with these notes from the former IB CS curriculum.

JSR Notes - FORMER CURRICULUM - 6.1.4 Describe how buses link the processor, the random access memory, the read-only memory and cache.

First a little bit on buses. Firstly, bus stands for bi-directional universal switch.

There are two general buses, internal and external. The external bus connects the core processing parts of the computer (the CPU, cache and memory) all the other parts: storage devices, such as hard drives and optical drives, and peripheral devices such as mouse, keyboard, and monitor. The internal bus is made up of the address and the data bus; together they allow for transferral of addresses and data between the CPU and the cache and RAM memory themselves.

In terms of the difference between the two internal buses, basically the address bus carries requests from the CPU to the RAM for information stored at various specific memory addresses. It is (in fact will have to be) the physical width of the system architecture - 32 wires wide, or 64 wires wide - so as to accommodate all the combinations of addresses being sent at one time.

Meantime, the data bus, most of the time, finds itself carrying data from the RAM; that data will either be in the form of instruction, or it will be data itself. And for objects, that "data" will be the references. But it's still data, carried on the data bus, even though the data is an address. And regarding the data bus' bi-directional nature, it at times will carry processed data back from the accumulator register to be stored in RAM.

The syllabus statement is more geared toward how these buses link the various core processing and primary storage components.