6.1.3 Describe the function of an interrupt register.
(No teaching notes for this one.)
Sample Questions:
(a) Define interrupt. [2 marks]
(b) Describe how an interrupt is detected and identified by the processor. [4 marks]
JSR Notes:
The function of the interrupt register is well explained in the text book. But to help you, here's a bit more, by way primarily of clarification.
Basically there are times when it is in everyone's best interest that the operation being executed in any give time be interrupted by some other process that should have priority. This is often because something urgent has happened, which has to be attended to right away. But often enough, it's just something that happens, and when it happens, it should be acknowledged and dealt with. And it can be a hardware interrupt or a software interrupt. Usually the urgent kinds of interrupts are hardware, and the non-so-urgent ones are software.
A hardware interrupt could happen when, for example, a paper misfeed at the printer has just happened. The computer could put that request for action in a queue and deal with whatever else it's dealing with first. But the sooner the user goes to attend to the printer the better. So the interrupt signal comes into the computer, through a specific interrupt "port", and the operating system, therefore recognizing the communication as being an interrupt, goes to the place in ROM where the specific information about how that specific computer can handle that specific interrupt, and executes it.
Software interrupts can be as simple as someone clicking a button in a GUI program. In order to respond to the user in a timely fashion, the CPU puts on the back-burner other things that it has on the go, and it executes the code coming in from the "mouse-down" "event". Certainly there is a hierarchy controlling which interrupt can trump which (rock, paper, scissors, anyone?), but as soon as is reasonably possible, the CPU will acknowledge and respond to the user's click.
In terms of the difference between queueing behavior and interrupt behaviour, think of the following analogy. Imagine a school cafeteria where all students actually queue up to be served at lunch. To make this analogy even more bizzare, when teachers come along, they are allowed to go to the front of the line - they can interrupt the queue, because they are more guaranteed to have work that they have to get back to. It is in the best interest for everyone at the school that they not waste their time waiting in lunch queues. And, like the first school I taught at, in Istanbul, it was not only for that reason, but out of repect for age and position. So in that same light, if the Director or other Administrators were to come along, they would be invited to interrupt the queue of teacher "interrupts". And though he never did, if the Prime Minister (or better yet, the Land Mafia boss that ran the school to lanunder his money...) came along for lunch, they would most certainly have been given top interrupt priority. In a computer, there are very many instructions that queue up to be processed when the CPU is able to do so. But there are other instructions which are more urgent, and so interrupt.
So what's actually held in the interrupt register? You guessed it, an address (or in the case of hardware interrupts, an address offset position - more on that below). With no current interrupt, the interrupt register is null. But when a certain signal is received, an address with (or offset to) the start of the required interrupt instructions is put in the interrupt register.
In the case of a hardware interrupt, it's actually an offset position of the correct interrupt-responding code be in the interrupt register. All hardware interrupts are "hard-wired" into the ROM, which is specific for the specific machine. In fact all the interrupt instructions are found in a certain contiguous space in ROM, of which the starting point is know. So, like the book describes, when a hardware interrupt is triggered, the code to be fetched from ROM will be: the known starting address + the offset value in the interrupt register.
Meantime, with a software interrupt, it's just a plain old address.
An interrupt can interrupt the processing of an interrupt that was triggered previously, but isn't finished yet. So the Control Unit of the CPU has to keep track of which interrupts have not been finished. It keeps these in a LIFO (Last In - First Out) order, and works its way down through the stack when it's able to.